1. Field of the Invention
The present invention relates to the field of design of electronic circuits, and more specifically to design and implementation of a power and area efficient hysteresis circuit having constant hysteresis for noise rejection.
2. Related Art
Receiver circuits are generally provided in various devices to propagate input signals received from external components (e.g., boards, devices, etc.) to internal components. Typically, a receiver circuit isolates the internal components from the external components, in addition to shifting logical voltage levels of input signal (generally higher) to required (lower) voltage level of the internal components.
One general requirement with receiver circuits is to consistently reject the noise signals that are often coexistent with the input signal. Noise rejection leads to advantages such as reliable recovery of the data represented by the input signals, etc., as is well known in the relevant arts.
In one approach, receiver circuits are implemented with hysteresis property to reject such noise. Hysteresis property generally refers to a behavior in which, as a parameter (in this case input voltage signal) is increased, the behavior (in this case output voltage of receiver circuit) makes a sudden jump (transition) at a particular value and as the parameter is then decreased, the jump back (transition) to the original behavior does not occur until a much lower value of the parameter. A receiver having such hysteresis property is often referred as a hysteresis receiver.
The manner in which a hysteresis design (within the receiver circuit) rejects noise associated with an input signal is further explained with the reference to the graphs of FIGS. 1A, 1B and 1C. In particular, FIGS. 1A and 1B respectively illustrate the hysteresis behavior of a hysteresis receiver in voltage and time domain, and FIG. 1C depicts the manner in which the hysteresis receiver rejects noise.
With respect to FIG. 1A, the X and Y axis respectively represent input voltage and output voltage of hysteresis receiver. The path corresponding to the arrow marks in the forward (from left to right) direction indicates that the output voltage jumps from 0 to Vdd at input voltage of Vih, and the voltage stays at Vdd as the input voltage is increased further. On the other hand, the path corresponding to the arrow marks in the reverse (from right to left) direction indicate that the output voltage falls from Vdd to 0 at input voltage of Vil (wherein Vil is less than Vih). The window Vih (upper bound) to Vil (lower bound) is referred to as the hysteris window. A time domain representation of hysteresis behavior is described below with respect to FIG. 1B for a clearer understanding.
FIG. 1B is a graph illustrating the variation of output voltage with respect to input voltage in time domain for a hysteresis receiver. Curve 150 represents the voltage of an input signal without noise and curve 160 represents the desired output signal. While the output signal is at logic low value, a transition in output signal from logic low to logic high requires that the voltage level of input signal increase to above Vih. Similarly, while the output signal is at logic high value, a transition in output signal from logic high to logic low requires that the voltage level of input signal fall below Vil.
As a result, any input fluctuation (due to noise) within hysteresis window 140 (region between Vil and Vih) is ignored by receiver and only transition beyond the hysteresis window is recognized as a valid change in input signal level, and the corresponding output signal is propagated to the internal components. Various noise signals are removed as a result. The reasons underlying the removal of noise (in FIG. 1B above) can be appreciated by considering a zero-hysteresis receiver (i.e., hysteresis window equaling 0). The operation of such a receiver is described below with reference to FIG. 1C.
FIG. 1C is a graph illustrating the propagation of false bits by a zero hysteresis receiver in the presence of noise in the input signal. Curve 170 represents input voltage signal with noise and curve 180 represents the corresponding output signal. Points 171, 172 and 173 represent variations in input signal crossing zero hysteresis line (Vil=Vih) due to noise as input voltage increased. Similarly points 176, 177, 178 represent points due to noise as input voltage is decreased.
False bits or glitches (fast transition) are generated as output signal at points 171-173 and 176-178. It may be appreciated that as the hysteresis window widens, input signal does not intersect Vil or Vih at points 171-173 and 176-178, hence preventing propagation of false bits or glitches to the internal component(s). Accordingly, there is a general need to implement receivers with hysteris (at least to eliminate noise).
Hysteresis receivers need to be implemented with various requirements. One requirement is that the hysteresis window be at least substantially constant (“constant hysteresis”). Another general requirement is that the implementations do not consume substantial area and/or electrical power. What is therefore needed is a power and area efficient hysteresis receiver having constant hysteresis for noise rejection.
In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.